Design for Testability of Sleep Convention Logic for memory applications

Abstract

Non-volatile memory,NVM storage is a type of computer memory that can retrieve stored information even after having been power off.Flash memory is the type of this memory.here we are using flash memory.these memory is used for floating type transistors.The commodity memory is a high performancememory and embedded memories alone memories these are used for flash which has rapid growth when we  go in the integrated chip. The flash memories have been Testedusing Conventional tests they are usually ad hoc.This is the procedure for testing which is expanded for certain designs.There is very much posibility of failure modes in this memories,automatic test equipment (ATE) is a test which is complicated and commonly seen. Production column and row address bit cell as basic design in SRAM. There will may be occurrence of sa0 and sa1 faults in anychip design, these faults will be overcome by using row,column address cells. we are making perfect location to store the data and making no cross sections of SRAMS. Extending of every cell checking for memory array and it gives verification of memory location. The row and column address buffer are used for picking the memory location. By comparing with previous method we used for the above two modules it gives accurate selection for memory location of cell check operation.