A High-Secure Vlsi Architecture For Advanced Encryption Standard (Aes) Algorithm
Abstract
In this paper we present a high-performance, high throughput, and area efficient architecture for the VLSI implementation of the AES algorithm. The sub keys, required for each round of the Rijndael algorithm, are generated in real-time by the key-scheduler module by expanding the initial secret key, thus reducing the amount of storage for buffering. Moreover, pipelining is used after each standard round to enhance the throughput. A prototype chip implemented using 0:35¹ CMOS technology resulted in a throughput of 232Mbps for iterative architecture and 1:83Gbps for pipelining architecture.
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