Design a High Speed and Area Efficient Carry Skip Ppa

Abstract

In this paper discussed about a carry skip adder (CSKA) structure with higher speed yet lower energy consumption compared with the conventional adder. In moreover, utilize multiplexer logic, the proposed structure make using NAND-NOR-Invert (NNI) and NOR-NAND-Invert (NNI) compound gates for the skip logic. The structure may be realized with both fixed and variable stage size styles, further improves the energy and speed parameters of the adder. Finally, a hybrid variable proposed adder structure, which lowers the power consumption affect the speed, is presented. The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.