Low Power Variation Tolerant Non Volatile Lookup Table Design

Abstract

Emerging non volatile memories (NVMs), such as PRAM, and RRAM, have been widely investigated to replace MRAM as the configuration bits in field-programmable gate arrays  for high security and instant power ON . This brief introduces a low-power variation-tolerant non volatile lookup table circuit to overcome the reliability issue in read and write the data. In present work RRAM cell is used to provide sufficient sense margin as a configuration bit and a reference resistor. A single-stage sense amplifier with voltage clamp is employed to reducing the power without impairing the reliability. The evaluation shows that 22% reduction in delay, 38% reduction in power, and the tolerance of variations of 2.5× typical RON or ROFF in reliability are achieved for the proposed non volatile lookup table.