A High Speed hybrid FIR Filter Architecture for Fixed and Reconfigurable Applications

Abstract

The main intent of FIR filters is to settle the impulse response zero in finite time. The filter may be discrete time or continuous time and analog or digital. In this paper for the purpose of better performance we use transpose form finite impulse response (FIR) filters. This filters are inbuilt pipe lined and it supports multiple constant multiplication (MCM) technique for saving estimation of filters. Based on the estimation analysis of transpose form of FIR filter the flow graph will be optimized for better complexity. Here transpose form does not directly support the block processing but there is a possibility of realization. In the proposed structure, there are two implementations one is less area delay product (ADP) and less energy per sample (EPS). Direct form FIR structure has less ADP and EPS than the proposed structure. So from the result of application specific integrated circuit synthesis, it shows that the proposed structure has block size 4 and filter length 64. This involves 42% less ADP and 40% less EPS than available FIR filter. Now let us see the result for the same block size and proposed structure involves 13% less ADP and 12.8% less EPS compared to proposed direct form block FIR structure.