Design of Redundant Binary Multipliers using Modified Partial Product Generator

P. Harikrishna, M. Pavitra

Abstract


Multiplication is one of the basic functions used in digital signal processing (DSP). Due to its high modularity and carry-free addition, a redundant binary (RB) representation can be used when designing high performance multipliers. The conventional RB multiplier requires an additional RB partial product (RBPP) row, because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding.

 

 This incurs in an additional RBPP accumulation stage for the MBE multiplier. In this paper, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW and hence, it saves one RBPP accumulation stage. Therefore, the proposed RBMPPG generates fewer partial product rows than a conventional RB MBE multiplier. Simulation results show that the proposed RBMPPG based designs significantly improve the area and High speed when the word length of each operand in the multiplier is at least 32 bits; these reductions over previous NB multiplier designs incur in 


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