High-Speed and Energy-Efficient Energy Efficient Carry Skip Adder Using Skip Logic

Abstract

here we present a carry skip adder (CSKA) structure has a higher speed but lower energy consumption with compared to conventional. The speed enhancement is applying by achieved incrementation and concatenation schemes to efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, utilizing instead of multiplexer logic, the proposed structure makes use of OR-AND-Invert (OAI) and AND-OR-Invert (AOI) compound skip logic gates. The structure may be realized with both variable stage size styles  and fixed stage size, where in the latter improves further  the energy and speed parameters for the adder. Finally, a variable hybrid latency extension of the proposed model, which Reduces power consumption considerably without impacting the speed, is presented. This utilizes extension a modified structure for parallel in increasing the slack time, and hence, enabling voltage further reduction. The proposed structures by comparing are assessed their speed, power, and with energy parameters those of other using a adders 45-nm static CMOS technology for a of supply voltages wide range. The results that are using HSPICE obtained simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest the structures among considered in this paper, while its product was almost energy–delay  the same as that of the Kogge–Stone prefix adder parallel with considerably area and power consumption low. Simulations on the variable latency proposed hybrid CSKA reveal reduction in the compared with the power consumption latest works in this field while high speed having a reasonably.