Babu, K Satish, (M.Tech) Associate Professor, India
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Vol 2, No 10 (2015): VOL-2_ISSUE-10_October_2015 - Research Articles
FPGA power Reduction by mux based clock gating considering a logic architecture
Abstract PDF
All published Articles are Open Access at https://journals.pen2print.org/index.php/ijr/
Paper submission: ijr@pen2print.org