Low Power Design of Double Ended Bit-lines with Read Decoupled 8T Static RAM Cell

Abstract

To propose a Double ended with read decoupled 8T Static RAM cell, uses the double connectivity of the bit-lines that help in fastly discharging the read data from the stored SRAM cell and improves the cell performance by reducing power consumption and  its delay. The proposed cell consumes low power and gives high performance than the existing single ended 8T SRAM-cell. 

In this analysis by varying the cell supply voltage and observed the scale down the voltage from 2.2v to 1.2v, maximum power reduction is observed in this proposed cell than existing single ended 8T cell.  That is power reduction of proposed cell is significantly reduced to 110.53uw to 316.59nw as compared to the existing cell power reduction is 247.22uw to 704.12nw. At particular cell supply voltage 2.2v, delay time of proposed cell is 35.231ps  then existing single ended 8t cell is 25.014ns. the entire design & simulation is implemented in the pyxis tool -130 nanometer scaling CMOS technology.

Application: SRAM have been wide range of applications, used in every memory used display devices for example handheld devices like mobile phones, laptops….etc.,