Power-Efficient Carry Select Adder

Abstract

To reduces the power consumption of data path we need to reduce Area of the adder. Carry Select Adder is one of the fast adder used in may data path applications. The proposed design is implemented without using multiplexer and RCA structure with Cin=1. This paper proposes on the logic operations in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA to study the data dependency and to identify redundant logic operations. To overcome this problem, a SQRT-CSLA based on CBL was proposed. However, the CBL-based SQRT CSLA design requires more logic resource and delay than the BEC-based SQRT-CSLA. We observe that logic optimization largely depends on availability of redundant operations in the formulation, whereas adder delay mainly depends on data dependence.