A Review: Comparison of Junction Based Transistor with Junctionless Transistor

Abstract

Now days, Digital Devices are designed using nanotransistor i.e. building block of any digital system. Scaling of gate in transistor device is considering main feature of fabrication technique. Smallest 10 nm Gate length devices were fabricated earlier. Now day’s Junctionless transistor is a uniformly doped nanowire without junctions with a wrap-around gate. The atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. In this paper review of structure, characteristics of junction transistor and junctionless transistor compared. This transistor in which there are no junctions and no doping concentration gradients. They have near-ideal sub threshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistor. Various simulators are available for simulation of junctionless transistor such as Silvaco ATLAS and Silvaco TCAD.