Design of Register File Using Reversible Logic

Abstract

Register file is the central perspective in PC memory unit. Eight bits (one memory unit) brings about a solitary enroll and 32 of such enlist make up an enlist record. In this paper we have displayed the outline of an entire enroll document utilizing reversible rationale plan. It comprises of decoder, multiplexer, memory unit, read and compose units. This has been confirmed utilizing Verilog HDL. Notwithstanding that, we have executed the enroll record in the outline of Content Addressable Memory (CAM) as an application.