Design of A Vedic Multiplier Using Area Efficient Bec Adder

Abstract

This paper presents a new design methodology for less delay and area efficient Vedic Multiplier based up on ancient Vedic Mathematic techniques. This paper presents a technique for N×N multiplication is implemented and gives very less delay and area efficient for calculating multiplication results for 16×16 Vedic multiplier.  In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva -Tiryagbhyam is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. Vedic multiplier is coded in Verilog HDL and stimulated and synthesized by using XILINX ISE software 14.7. Further the design of array multiplier is compared with the proposed multiplier in terms of l delay and area.