High performance and high efficiency DET flip flop by using Clock gating techniques

Abstract

Dual edge triggered (DET) flip-flops achieve the same data rate as single edge triggered (SET) flip-flops at half the clock frequency, which can lead to reduced power dissipation of synchronous logic circuits. The cost of this reduction is higher circuit complexity of DET flip-flops which usually have more transistors and more internal nodes than SET flip-flops. In this paper, a novel Clock gating  flip-flop (FF) design for high speed applications is presented. . Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop.