Fault Tolerant Parallel Filters Based on ErrorCorrection Code

Abstract

In today’s world, there is a great need for the design of low power and area efficient high-performance DSP system. FIR filter is considered to be the fundamental device in the broad application of wireless as well as the video and image processing system. As technology scales, it enables more complex systems that incorporate many filters. In those complex systems, it is common that some of the filters operate in parallel, for example, by applying the same filter to different input signals. Recently, a simple technique that exploits the presence of parallel filters to achieve fault tolerance has been presented. In this brief, that idea is generalized to show that parallel filters can be protected using error correction codes (ECCs) in which each filter is the equivalent of a bit in a traditional ECC This new scheme allows more efficient protection when the number of parallel filters is large. Finally, both the effectiveness in protecting against errors and the cost are evaluated for an FPGA implementation.