Design and Analysis of Low Power High Performance 13T SRAM for Ultra Low Power Applications

Abstract

Rapid advances in the field of very large scale system designs brought memory circuits are continuously regulated and in turn, more number of cells could made possible to integrate on small chip. However in Nano scale 13T SRAM there is large variation of threshold voltage occurs. To solve threshold voltage variation problem in 13T SRAM in this paper we proposed the sleep approach based 13T SRAM cell and later we introduce a sleep approach based 13T SRAM which effectively reduces the problem. This paper was carried out by using Tanner EDA Tools