Efficient Design of Hybrid Lut /Multiplexer Fpga Logic

Abstract

Hybrid configurable logic block architectures for area-programmable gate arrays that include a mixture of lookup tables and hardened multiplexers are evaluated closer to the goal of higher logic density and place discount. Multiple hybrid configurable good judgment block architectures, each nonfractural and fractural with varying MUX:LUT logic element ratios are evaluated throughout  benchmark suites (VTR and CHStone) the use of a custom tool waft which includes LegUp-HLS, Odin-II front-quit synthesis, ABC good judgment synthesis and era mapping, and VPR for packing, placement, routing, and structure exploration. [1] Technology mapping optimizations that concentrate onthe proposed architectures also are carried out inside ABC. Experimentally, we show that for nonfracturable architectures, with none mapper optimizations, we obviously save as much as ∼eight% region post place and path; both accounting for complicated logic block and routing region while retaining mapping depth. With architecture-conscious generation mapper optimizations in ABC, extra area is saved, put up-location-and-path. For fracturable architectures, experiments display that simplest marginal profits are seen after region-and-path as much as ∼2%. For both nonfracturable and fracturable architectures, we see minimal impact on timing performance for the architectures with nice location-performance.