Novel Dsp Accelarator Architecture Based On Carry Save Arithmetic

Abstract

In the virtual signal processing (DSP) area, Hardware acceleration is proved an exceptionally promising implementation strategy. Instead of adopting a monolithic software-specific integrated circuit layout technique, a unique accelerator structure comprising bendy arithmetic components that guide the execution of a massive set of operation templates discovered in DSP kernels is introduced. One of its essential peculiarity is to enable computations to be aggressively performed with deliver-shop (CS) formatted statistics. Incorporation of Error Tolerant Adder is some otherspeciality. Advanced arithmetic layout ideas, i.E., recoding techniques, and more desirable arithmetic components are utilized permitting CS optimizations to be executed in a bigger scope than in previous approaches.