Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT Using Verilog HDL

Abstract

A high speed word level finite field multiplier in F2 m using redundant representation is proposed. For the class of finite field that there exists a type I optimal normal basis, the new architecture has sign can  higher speed compared to previously proposed architectures using either normal basis or redundant representation at the expense of moderately higher area complexity . One of the unique features of the proposed multiplier is that the critical path delay is not a function of the eld size nor the word size. It is shown that the new multiplier out-performs all the other multipliers in comparison when considering the product of area and delay as a measure of performance. VLSI implementation of the proposed multiplier in a 0:18m CMOS process is also presented.