Condition Probability Estimation for Low Error Energy Efficient Fixed Width Booth Multiplier with Sign Digit

Abstract

Multipliers play an important role in digital signal processing and various other applications. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets – high speed, low power, regularity of layout and hence less area. In any multiplication algorithm, the operation is decomposed in a partial product summation. Each partial product represents a multiple of the multiplicand to be added to the final result. Here Radix-4 booth multiplier is used to reduce number of partial products. The Wallace tree addition method is used in high speed designs in order to produce two rows of partial products that can be added in the carry look ahead adder, which reduces number of steps to be performed. Also critical path and the number of adders get reduced when compared to the carry save adder. The Radix-4 booth multiplier with Wallace tree addition design is coded with Verilog, synthesized and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.