Design of Fast and Low Area Pre-Encoded Multipliers Based on NR8SD Encoding technique for DSP/Multimedia applications

Abstract

In this paper, we introduce an architecture of Non-Redundant radix-8 Signed-Digit (NR8SD) encoding technique, which uses the digit values{-3,-2,-1,0,+1,+2,+3,+4} or {-4,-3,-2,-1,0,+1,+2,+3} is proposed leading to a multiplier design with less complex partial products implementation compared to NR4SD multiplier.

NR4SD multiplier is also more area efficient compared to MB multiplier, which uses the digit values {-2,-1,0,+1} or{-1,0,+1,+2} that leads to fast multiplication than the conventional Modified Booth Multiplier. These pre-encoded multipliers are based on off-line encoding of generating less number of coefficients for DSP applications.

Keywords: Modified Booth Encoding, Non Redundant Radix-4 Signed Digit (NR4SD)pre encoding multiplication by constants, Non Redundant Radix-8 Signed Digit (NR8SD)pre encoding multiplication ,common sub expressions sharing, Add-Multiply operation, arithmetic circuits.