Design andStudy of On-chip Bus with Open Core Protocol Interface

Abstract

As increasingly more IP cores are integrated intoa SOC layout, the conversation flow among IP coreshas expanded considerably and the performance of the on-chipthe bus has become a dominant aspect of the performance ofa system. The on-chip bus design may be divided into parts, particularly the interface and the internal architecture ofthe bus.In this work, the well-described interface well known Open Core Protocol (OCP) is adopted, and the internal bus architecture is designed. The Open Core Protocol(OCP) is a middle-centric protocol which defines an excessive-performance, the bus-unbiased interface between IP cores that reduces layouttime, design threat, and production expenses for SOC designs. The essential belongings of OCP are that it may be configured with appreciating thesoftware required. The OCP is chosen because of its advanced supporting features which include configurable sideband control signalingand check harness alerts whereas as compared to other middle protocols. The OCP defines a point-to-point interface between communicating entities including IP cores and bus interface modules. One entity acts as the master of the OCP instance, and the alternative asthe slave. Only the master can present instructions and is the controlling entity. The slave responds to commands provided to it, either by means ofaccepting data from the master or importing data to the master.