Trustworthy Low-Power Multiplier Design using Fixed-Width Replica Redundancy Block: A Review

Abstract

A reliable low-power multiplier design by adoptingalgorithmic noise tolerant (ANT) architecture with truncatedbinary multiplier to build the fixed width reduced precisionreplica redundancy block (RPR).The proposed ANT architecture canmeet the demand of high precision, low power consumption, and area efficiency. We design the fixed-width RPR with errorcompensation circuit via analyzing of probability and statistics. Using the partial product terms of input correction vector and minorinput correction vector to lower the truncation errors, the hardware complexity of error compensation circuit can be simplified.