Low power 16 bit ALU design using Full adder and Multiplexer

Abstract

This project describes the techniques for fabricating a high speed ALU using pass transistor logic. Double pass transistor logic is shown to improve the circuit performance at reduced supply voltage. Using DPL technique a 16 bit ALU is designed with the help of multiplexers and full adder. In the existing method full adders and multiplexers were designed using PTL method. The main component in the ALU is full adder. In CMOS method eight transistor full adder and CMOS based multiplexers are used. By reducing area and by using DPL based multiplexers low power ALU is attained. In the implementation of ALU using DPL method, the power and area are reduced compared to PTL method. With the increase in the bit size there are a number of uses, Speed of the processor increases as it can accommodate large bit size and number of applications increases. Results are observed using Microwind and Digital Schematic.