Graph-Based Transistor Network Generation Method for Super gate Design

Abstract

Transistor organize improvement speaks to a compelling method for enhancing VLSI circuits. This paper proposes a novel technique to naturally create systems with negligible transistor check, beginning from an irredundant entirety of-items articulation as the info. The technique can convey both series– parallel (SP) and non-SP switch game plans, enhancing speed, control scattering, and range of CMOS entryways. Exploratory outcomes exhibit expected picks up in examination with related methodologies.