Performance Analysis of On-Chip Memory Architecture Exploration of Embedded Processor

Abstract

Embedded systems are regularly intended for one or a couple of target applications, taking into account customization of the system design for the coveted system objectives, for example, execution, power and cost. The memory subsystem will continue to show noteworthy bottlenecks in the plan of future embedded systems-on-chip. Utilizing advance information of the application's instruction and information conduct, it is conceivable to redo the memory engineering to meet shifting system objectives. On one hand, different applications display shifting memory conduct. On the other hand, an extensive assortment of memory modules permits plan implementations with an extensive variety of cost, execution and power profiles. The embedded system designer would thus be able to investigate and select custom memory structures to fit the constraints of target applications and outline objectives. In this paper we introduce a diagram of late research in the territory of memory engineering customization for embedded systems.