Implementation of UART based on BIST(Built in self test) Architecture

Bodapati Lakshmi Durga, G.Srinivasa Rao, CH. Balaswamy


Testing of VLSI chips is changing into significantly complicated day by day as a result of increasing exponential advancement of NANO technology. BIST is a technique that enables a system to check mechanically itself with slightly larger system size. This paper targets the introduction of Built-in self test (BIST) and Status register to UART. Asynchronous serial communication is usually implemented by Universal Asynchronous Receiver Transmitter (UART), mostly used for short distance, low speed, low cost data exchange between processor and peripherals. The BIST used here have two modes actually i.e. test mode and UART mode. This technique generate random test pattern automatically, so it can provide less test time compared to an externally applied test pattern and helps to achieve much more productivity at the end. Simulation results for BIST enabled UART are observed by Xilinx ISE design suite.

Full Text:


Copyright (c) 2018 Edupedia Publications Pvt Ltd

Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.


All published Articles are Open Access at 

Paper submission: