Design of Low Power & High Speed Parallel Prefix Comparator

V.Venkata Arjun, Lakshmi Prasad.Ch


In this paper we proposes a comparator design using  digital CMOS cells featuring wide-range and high-speed operation. The Comparison is most basic arithmetic operation that determines whether one number is greater than, less than or equal to the other number. Our comparator uses a novel scalable parallel prefix structure that leverages the comparison outcome of the MSB, proceeding bitwise towards LSB only when the comparison bits are equal. This comparator is composed of locally interconnected CMOS gates with a maximum fan-in of five and fan-out of four, independent of comparator bandwidth. Comparator is most fundamental component that performs comparison operation. Comparison between modified and existing 8-bit binary comparator using parallel prefix designs is calculated by simulation performed at 90nm technology in DSCH, Microwind Tool and simulated with Xilinx ISE13.1. The main advantages of our proposed design are high speed and power efficiency, maintained over a wide range.

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