Design A Low-Latency Cryptography Based Viterbi Algorithm Architectures

Abstract

Basically, Viterbi algorithm [V.A] is used in many applications like satellite communication, cellular relay and wireless local area networks. This algorithm is mainly applied to the decoding conventional codes and also to automatic speech recognition and storage devices. In Viterbi algorithm architecture we are using error detection scheme which depends on the low complexity and low latency. The main advantage of this proposed system is that it gives reliable requirements and as well as performance degradation. Here we use three variants in the system which recomputed with the encoded operands. Now this system is modified by detecting the both transient and permanent faults [P.F] which are mixed with signature based methods. Here in this paper we are using instrumented decoder architecture for the purpose of extensive error detection assessments. For the purpose of bench mark we are implementing the both application specific integrated circuit and field programmed gate array. Depend upon the reliability objectives and performance degradation tolerance, the proposed system is utilized.