On the Analysis and Design of Low Power, High Speed n-bit Decoders Using MLD

Abstract

Decoders are one of the most important circuits used in communication channels. Different approaches have been proposed for n-bit conventional decoders design. In this article, we have proposed novel design line decoders, combining transmission gate logic, pass transistor dual-value logic and static CMOS. Two novel topologies are presented for the 2-4, 3-8 and 4-16 decoders: a 14-transistor topology aiming on minimizing transistor count and power dissipation and a 15-transistor topology aiming on high power- delay performance. Both a normal and an inverting decoder are implemented in each case, yielding a total of four new designs. Furthermore, four new 4-16 decoders are designed, by using mixed-logic 2-4 pre-decoders combined with standard CMOS post-decoder. All proposed decoders have full swinging capability and reduced transistor count compared to their conventional CMOS counterparts. Finally, a variety of comparative simulations at the 65 nm shows that the proposed circuits present a significant improvement in power and delay, outperforming CMOS in almost allcases.