Design of threshold logic gate using Testing Delay in Current Mode

Abstract

Current mode is a popular CMOS-based implementation of threshold logic functions, where the gate delay depends on the sensor size. The power of the threshold gate design style lies in the intrinsic complex functions implemented by such gates, which allow system realizations that require less threshold gates or gate levels than a design with standard logic gates. This paper presents a new implementation of current mode threshold functions for improved gate delay and switching energy. An analytical method is also proposed in order to identify quickly the sensor size that minimizes the gate delay. Simulation results on different gates implemented using the optimum sensor size indicates that the proposed current mode implementation method outperforms consistently the existing implementations in delay as well as switching energy. The proposed architecture of this paper analysis the logic size, area and power consumption by using  backend design.