Design of Proficient Adders for Multipliers using CMOS and GDI Techniques

Abstract

High speed and low power adder circuits are highly demanded in VLSI design. As the days pass by, the advancement in the innovation is becoming more faster. In this paper, a new approach for high speed and low power adder design, optimization of Area, Power and Delay is proposed. The proposed work deals with the construction of high speed adder circuits. Design and modeling of various adders like Ripple Carry Adder, Kogge Stone Adder, and Brent Kung Adder is done by using CMOS and GDI logic and comparative analysis is coated.