Optimization of 2-4, 4-16 Decoders and 2-Bit Comparator

Abstract

A mixed-logic design method for line decoders, combining transmission gate logic, pass Transistor dual-value logic and static CMOS. Two novel topologies are presented for the 2-4 decoder: a 14-transistor topology aiming on minimizing transistor count and power dissipation and a 15-transistor topology aiming on high power- delay performance. Both a normal and an inverting decoder are implemented in each case, yielding a total of four new designs. four new 4-16 decoders are designed, by using mixed-logic 2-4 pre decoders combined with standard CMOS post-decoder. All proposed decoders have full swinging capability and reduced transistor count compared to their conventional CMOS counterparts. The proposed circuits present a significant improvement in power and delay, outperforming CMOS in almost all cases .comparator circuit is designed using mixed logic line decoders.