A Memory Efficient Vlsi Iplementation Of Golay Codes

M. Kathyayani, M. Gowthami, P. Sandhya Rani, O. Vijaya Durga, A. Radha


In today’s world storing numerous data or information efficiently is a significant issue because of limited storage. Every moment we need to transfer large volume of information soundly and correctly. A storage space/memory storage required to store this information. The way of communication which is also constricted with confined communication lines. The proposed system consists of a cyclic redundancy check-based encoding scheme and implemented an efficient encoding algorithm for both the Golay Codes. Golay Code is a type of Error Correction Code and its performance is very nearer to Shanon’s limit. Good error correcting performance enables reliable communication. The binary Golay Code (G23) is represented as (23, 12, 7) while the extended binary Golay Code (G24) as (24, 12, 8). High speed with low-latency architecture has been designed and implemented for Golay encoder without incorporating linear feedback shift register. Our proposed Golay code technique is much more efficient than most of the other existing techniques. The results obtained significant improvements over previous/existing work.

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