Low power and high speed optimized 4-bit array multiplier using GDI technique

Abstract

Multipliers are the most commonly used elements in today’s digital devices. It plays a very important role in some applications such as Digital Signal Processing and Image Processing applications. One of the basic multiplier is Array Multiplier. This multiplication is based on basic mathematic multiplication. Array multiplier can be implemented by using many techniques like CMOS,PTL,DPL etc. To overcome the limitations of these techniques a new technique is implemented in this paper, called Gate Diffusion Input (GDI). This paper aims at design of an optimized low power and high speed 4-bit array multiplier by using GDI Technique. With this technique total propagation delay, power consumption and transistor count are decreased compared to CMOS technology. The results give comparative analysis of CMOS and GDI techniques about power, transistor count and time delay parameters.