Design of Low Power and Low Latency Novel Scheme for Network on Chip

Abstract

Network-on-chip (NoC) has emerged as a scalable and promising solution to global communications within large multi core systems. The NoC with virtual point-to-point connections (VIP)is the existing, the proposed Novel  scheme can reduce the latency along with the power. A path allocation algorithm is proposed in this paper to determine VCS connections and circuit-switched connections on a mesh connected NoC, such that both communication latency and power are optimized. A novel switching mechanism, called virtual circuit switching, is proposed to intermingle with circuit switching and packet switching. Flits travelling in virtual circuit switching can traverse the router with only one stage. In addition, multiple virtual circuit-switched (VCS) connections are allowed to share a common physical channel.