Performance of Dual Edge Triggered (DET) Flip-Flops Using Multiple C-Elements

Abstract

Design of Dual-edge triggered (DET) flip-flops that exhibit unique circuit behavior owing to the use of C-elements. Five novel DET flip-flops are presented including two high-performance designs and designs that improve upon common Latch-MUX DET flip-flops so that none of their internal circuit nodes follow changes in the input signal. A common characteristic of the presented flip-flops is their low energy dissipation due to glitches at the input .The presented analysis estimates the area and speed. These DET flip-flops are compared to existing DET flip-flops using simulation in a high performance 180 nm CMOS technology and are shown to have superior characteristics such as power and power-delay product (PDP) for a range of switching activities,by using MICROWIND/DSCH 180 nm technology and simulation results obtained by using HSPICE 180 nm technology. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and transistor count with respect to other designs.