High Speed Vlsi Architecture For Proposed Novel Adiabatic Encoder And Decoder

Abstract

In this paper Sample adaptive encoder architecture is used as new in-loop filtering block. Exhaustive operations are performed to get the optimum AO parametersbecause of the huge amount of samples. In this paper we propose an High speed and low power Encoder Decoder of rate ½ convolutional coding with a constraint length K = 3. At last we justify that using both logics in one Integrated Circuit (IC) we can create a high speed and low power Proposed encoder decoderwith some extra hardware area