A Study on Design and Implementation of Fault Tolerant Parallel FFTs using Error Correction Codes

Abstract

The intricacy of correspondences and flag processsing circuits expands each year. This is made conceivable by the CMOS innovation scaling that empowers the joining of an ever increasing number of transistors on a solitary gadget. This expanded many-sided quality makes the circuits more helpless against blunders. In the meantime, the scaling implies that transistors work with bring down voltages and are more powerless to blunders caused by commotion and assembling varieties. Delicate mistakes represent a dependability danger to current electronic circuits. This makes insurance against delicate blunders a prerequisite for some applications. Interchanges and flag handling frameworks are no exemptions to this pattern. For a few applications, a fascinating alternative is to utilize algorithmic-based adaptation to internal failure (ABFT) procedures that endeavor to misuse the algorithmic properties to distinguish and remedy mistakes.