Design a High Speed and Area Efficient Multiplier Using Adiabatic Logic



Digital multipliers can be included among the highly significant arithmetic functional units. High speed and low power consumption is one of the significant objectives of design in integrated circuits. As multipliers are widely utilized in circuits, the multipliers must be efficiently designed. Here, a design of multiplier with aging aware is existed with adaptive hold logic (AHL). Complex numbers multiplication is a arithmetic operation to be performed with less power consumption and high speed in systems which having high performance such as wireless communications. Hence, in this paper, two possible architectures are proposed. The architecture of proposed multiplier with minimum path delay is used in the implementation of complex multiplier. The architectures for the three multiplier solution and four multiplier solution of complex multiplier for complex numbers multiplication are coded and implemented through Xilinx ISE.  

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