Design of High Speed ALU Using Adaptive Logic

Abstract

In this paper, we introduce high speed architecture for 32-bit ALU using Adaptive logic technique. Adaptive logic  is  one  of  the  fastest  and  innovative  logic  that  has  been  implemented  in  digital  circuit . Adaptive logic is  implemented  using  the CMOS  technology. It works very effectively in both threshold and sub – threshold regions which uses Timing-error-detection (TED)-based systems is been shown to reduce power consumption or increase yield due to reduced margins. Reducing voltage in the circuit results in slow operation that incurs more delay. Generally delay is caused due to slow operation that results in error based upon the conditions. Canary circuit has been designed for error detection and error correction approach for reducing the power and voltage in a digital circuit. Adaptive logic, which is nothing but modified canary circuit with add-on components to canary circuit have been designed with dual latch phase in each stage. A combination of  XOR gate and flip-flop around each stage is added for the verification of correct operation. The entire architecture was modeled using Verilog HDL with the help of XILINX ISE tool.