Design and Implementation of 17 Transistors Full Adder cell

Abstract

Implementing new logic circuit in digital electronics is a big challenge. Many conventional logic circuits were developed and are being used successfully. But, by introducing new logic for the same function may have less number of transistors or achieve high speed or less power consumption or trade of between these parameters. Because of the above advantages a designer always looks for introducing new logics either for the existing circuits or for new circuits. In this paper, A 17 transistor full adder cell is proposed. Fifteen states of the arts 1-bit full adders are taken for comparison and one proposed full adder is simulated with TSPICE using 0.18 micro meter CMOS Technology with the supply voltage of 1.8v.