Design And Analysis Of Multi-Threshold Cmos Full Adder Using 90nm

Abstract

High rate of power consumption in the digital integrated circuit is the major field of concern in the development of VLSI circuits. Demand of higher speed multiple operations and smaller process geometry contributes in the leakage power. So today leakage power consumption is the most important source of power dissipation rather than run time power consumption. Previously many techniques have been proposed for the leakage reduction. Amongst all MTCMOS technique carries the property of being most efficient in leakage reduction. In this paper we are going tost all MTCMOS technique carries the property of being most efficient in leakage reduction. In this paper we are going to analyze the different types of low power adder circuits with different types of low power design methodologies. The comparison results have also been displayed in this paper. The circuits are simulated in 90nm CMOS technology using tanner EDA simulator.