Design of full adder using VHDL

Rashmi Kumari, Swapnil Rai, Subha Kaushik

Abstract


In thi paper we are going to design full adder using VHDL. The acronym VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. This paper includes the design of full adder with behavioral modelling in VHDL, truth table and results are verified with simulation software Xilinx.

Keywords


VHDL; VHSIC; full adder; behavioral modelling; simulation; xilinx

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Copyright (c) 2015 Rashmi Kumari, Swapnil Rai, Subha Kaushik

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