Novel VLSI Architecture of Fir with Lut Less Method Using Distributive Arithmetic for DSP Applications

Abstract

 Adder and multipliers are used in many processors to accomplish fast arithmetic function. Many different adder architecture designs have been developed to increase the efficiency of the adder. A filter is used to pass a specific band of frequency. Depending on the response of the system, digital filters can be classified into Finite Impulse Response (FIR) and Infinite Impulse Response (IIR). Digital filters are widely used in many digital signal processing applications. Therefore digital filtering is one of the basic need of digital signal processing. In traditional fir filter consumes more power and area because of multipliers usage to avoid this disadvantage in this paper designs a new approach to design a fir filter by using distributive arithmetic method in lutless method. In this paper fir with traditional adder is existed design and fir filter using parallel prefix adder is the proposed design. Parallel prefix adders are the good adder for fast execution it is reduce the complexity of the multiplication process, it causes to reduce the power and area of the design Performance of all adder designs. And this project implemented for 64 bit lut less fir structure; these structures are synthesized on Xilinx 12.3 ISE tool.