Data Encoding Techniques for Lower Power Dissipation in Network on Chip using parity encoder

Abstract

In this project, a low-power data encoding scheme is proposed. In general, system-on-chip (soc) based system has so many disadvantages in power-dissipation as well as clock rate wise such transfer the data from one system to another system in on-chip. At the same time, a higher operated system does not support the lower operated bus network for data transfer. However an alternative scheme is proposed for high speed data transfer. But this scheme is limited to SOCs. Unlike soc, network on- chip (NOC) has so many advantages for data transfer. It has a special feature to transfer the data in on-chip named as transitional encoder. Its operation is based on transitions of input data. At the same time it supports systems which are operated at higher frequencies. The proposed system yields lower dynamic power dissipation due to the reduction of switching activity and coupling switching activity when compared to existing system. The proposed schemes are general and transparent with respect to the underlying NoC fabric (i.e., their application does not require any modification of the routers and link architecture).