Performance Analysis of Five Port Router Network for VLSI based Network on Chip

chalavadi Raghavendrarao, S. T. Mrudula


In his paper we attempt to give a networking solution by applying VLSI architecture techniques to router design for networking systems to provide intelligent control over the network. Networking routers today have limited input/output configurations, which we attempt to overcome by adopting bridging loops to reduce the latency and security concerns. The approach will results in increased switching speed of routing per packet for both current trend protocols, which we believe would result in considerable enhancement in networking systems.


Network-on-Chip ; Simulation Router; FIFO; FSM; Register blocks

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Copyright (c) 2015 chalavadi Raghavendrarao, S. T. Mrudula

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