A Unique Low-Power Implementation of 4-2 Compressor in High Speed Multiplier

Abstract

On using these Compressors in the multiplier, the number of interconnections gets reduced, which further produces quick results, along with consuming lesser power. The concept of these compressors for improving the performance of the multiplier is done on transistor level. The performance of these different designs is compared and the observation is that the usage of compressor makes the process more energy efficient and faster as compared to the traditional methods. The delay and power-delay product (PDP) is compared with earlier Wallace and Dadda Multipliers, implemented with 4-2 Compressors and without compressors, and is proven to have minimum delay and PDP.