A Novel Approach to Design a Scalable Comparator using QCA Based Parallel Prefix Tree
Abstract
COMPARATORS are the key design elements for a wide range of applications like scientific computation (graphics and image/signal processing),test circuit applications (jitter measurements, signature analyzers, and built-in self test circuits) and for general-purpose processor components (associative memories, load-store queue buffers, translation look-aside buffers, branch target buffers) and many other CPU argument comparison blocks .In this project a 32 bit comparator architectures is designed by using parallel prefix structure.
Full Text:
PDFCopyright (c) 2015 Yammanuru Sruthi, K. Pakeerappa
![Creative Commons License](http://licensebuttons.net/l/by-nc-sa/4.0/88x31.png)
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.
All published Articles are Open Access at https://journals.pen2print.org/index.php/ijr/
Paper submission: ijr@pen2print.org