Accomplishment of Dynamic Double-Tail Comparator intended for High Speed Applications

Abstract

In the present scenario, need for ultra low-power, area efficient and high speed analog-to-digital converters (ADCs) is pushing toward the use of dynamic Clocked regenerative comparators to improve the power efficiency and speed. In this work , we modified the structure of the Dynamic Double-Tail Comparator by adding few additional transistors to the existing structure. The proposed modified Double-Tail Dynamic Comparator is used for fast operations even in very small supply voltages. We can implement the proposed structure and existing structures of Dynamic Comparator in Mentor Graphics Tool. From simulation results in 0.18-μm CMOS technology, we find that the proposed design yields less Delay than the existing structures.